The semiconductor memory industry has been introducing various SRAMs. Of these SRMs an SRAM is known in which a pair of bit lines are precharged to a HIGH level (V.sub.dd) and a word line is made active to read out a bit of data stored in a memory cell. One of the bit line pair, selected on the basis of the stored data, discharges through the memory cell, thereby creating a difference in potential between the bit line pair. Such a potential difference is amplified by a sense amplifier. If the word line is left active, then the potential of the bit line that is still discharging will keep falling and eventually reach the ground level (zero volt). This is because that electric charges held by the bit line in question keep vanishing. As a result, the potential of the bit line considerably drops, thereby producing the problem that much charging current is required at the next precharge cycle.
Japanese Patent Application, published under No. 60-61986, attempts to offer a solution to the above mentioned problem. In accordance with this technique, a memory cell is separated from a bit line pair by making a word line inactive, before the potential of one bit line drops to the ground level and at a point in time when the output potential of a sense amplifier becomes definite. As a result of such arrangement, the drop in potential becomes controllable and power consumption during the precharge process can be reduced. Establishment of the sense amplifier's output potential is detected by, for example, a sensing circuit with a circuit threshold of 1/2 V.sub.dd.
In a CMOS SRAM having a latch-type sense amplifier, amplification operations by such a sense amplifier is permitted to start when the potential of one bit line falls by V.sub.tp (i.e., the threshold voltage of a PMOS transistor) from V.sub.dd. After the potential of the bit line falls below a difference of V.sub.dd -V.sub.tp, the sense amplifier can keep operating even if the memory cell is separated from the bit line pair and the sense amplifier itself is separated from the bit line pair, and the output potential of the sense amplifier becomes definite.
The above-described SRAM, however, suffers from some problems. For instance, in such an SRAM, it is not until the output potential of a sense amplifier becomes definite that a word line becomes inactive. Because of this, the drop in bit line potential cannot be controlled successfully. Another problem is that in some SRAM internal structures the sense amplifier may reduce the bit line potential with high-drive capability. Furthermore, the drop in bit line potential may be caused by all the memory cells belonging to a single row.